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參數(shù)資料
| 型號： | HD74LV595A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Shift Registers with 3-state Outputs |
| 中文描述： | 8位移位寄存器3態(tài)輸出 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 82K |
| 代理商： | HD74LV595A |
HD74LV595A
8-bit Shift Registers with 3-state Outputs
ADE-205-281 (Z)
1st Edition
April 1999
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register state will always be one clock pulse ahead of the storage
register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Output current
±
6 mA (@V
CC
= 3.0 V to 3.6 V),
±
12 mA (@V
CC
= 4.5 V to 5.5 V)
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