Rev. 2.0, 09/02, page
vi
of
xviii
Contents
Section 1 Overview ....................................................................................... 1
1.1
Features.......................................................................................................................2
1.2
A List of Specifications................................................................................................9
1.3
Block Diagram.............................................................................................................10
1.4
Processing States .........................................................................................................13
1.4.1
Power On........................................................................................................13
1.4.2
Initial States (when Specified Power is Supplied).............................................13
1.4.3
Reset State (when Low Level is Input to
5(6(7
Pin) ......................................14
1.4.4
UGM Initialization State..................................................................................14
1.4.5
Normal Operating State...................................................................................14
Section 2 Pins................................................................................................ 15
2.1
Pin Configuration.........................................................................................................15
2.2
Pin Arrangement..........................................................................................................16
2.3
Pin Functions...............................................................................................................17
2.4
System Control Pins.....................................................................................................23
2.4.1
Operating Mode Pins.......................................................................................23
2.4.2
Clock Pins.......................................................................................................23
2.4.3
Reset Pin.........................................................................................................25
2.4.4
Power Supply Pin............................................................................................25
2.5
CPU Interface Pins.......................................................................................................26
2.5.1
CPU Writes.....................................................................................................26
2.5.2
CPU Reads......................................................................................................26
2.5.3
DMA Writes....................................................................................................27
2.5.4
Interrupts.........................................................................................................28
2.6
UGM Interface Pins.....................................................................................................28
2.7
Display Interface Pins..................................................................................................28
2.7.1
Display Signal Output .....................................................................................28
2.7.2
Video Encoder Interface..................................................................................29
2.7.3
CRT Interface..................................................................................................29
2.7.4
D/A Converter.................................................................................................29
2.8
Video Interface Pins.....................................................................................................30
2.8.1
Video Input Interface.......................................................................................30
Section 3 UGM Architecture ......................................................................... 33
3.1
Features.......................................................................................................................33
3.2
Q2SD Access...............................................................................................................34
3.2.1
UGM Access Priority ......................................................................................34
3.2.2
UGM Access by the CPU................................................................................35