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參數(shù)資料
| 型號(hào)： | HD4074849TF |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁數(shù)： | 87/125頁 |
| 文件大?。?/td> | 471K |
| 代理商： | HD4074849TF |
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HD404849 Series
87
Notes on Use:
Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.
Setting the serial interrupt request flag (IFS: $023, bit 2): If the state is changed from transfer to another
by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register A write or STS instruction execution must be programmed to be executed after
confirming that the
SCK
pin is at 1, that is, after executing the input instruction to port R2.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
Serial Mode Register A (SMRA: $005)
Serial Mode Register B (SMRB: $028)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Miscellaneous Register (MIS: $00C)
Serial Mode Register A (SMRA: $005):
This register has the following functions (figure 70).
R2
1
/
SCK
pin function selection
Transfer clock selection
Prescaler division ratio selection
Serial interface initialization
Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to
the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is
performed during data transfer, the data transfer is discontinued and the serial interrupt request flag (IFS:
$023, bit 2) is set.
Written data is valid from the second instruction execution cycle after a write operation, so the STS
instruction must be executed at least two cycles after a write operation.
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