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參數(shù)資料
| 型號(hào)： | HD4074849TF |
| 廠商： | Hitachi,Ltd. |
| 元件分類(lèi)： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁(yè)數(shù)： | 12/125頁(yè) |
| 文件大小： | 471K |
| 代理商： | HD4074849TF |
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HD404849 Series
12
bit3
bit2
bit1
bit0
Interrupt control bits area
$000
$003
SMRA $005
SRL $006
SRU $007
TMA $008
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC1 $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
TMD1 $010
TRDL/TWDL $011
TRDU/TWDU $012
TMB2 $013
TMC2 $014
TMD2 $015
AMR $016
ADRL $017
ADRU $018
LCR $01B
LMR $01C
LOR3 $01F
$020
PMRB $024
PMRC $025
ESR1 $026
ESR2 $027
SMRB $028
SSR $029
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR6 $036
DCR7 $037
V $03F
PMRA $004
$023
R2
2
/SI
R2
3
/SO
R2
1
/
SCK
Serial transmit clock speed selection 1
Serial data register (lower digit)
Serial data register (upper digit)
Timer A/time base
Auto reload
on/off
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (upper digit)
PMOS SO control
Pull-up MOS control
Auto reload
on/off
Timer C output mode selection
Analog channel selection
A/D data register (lower digit)
A/D data register (upper digit)
A/D conversion period
*
1
*
2
LCD power switch
LCD duty cycle selection
LCD display on/off
R7/SEG17–20
R6/SEG13–16
R0
2
/INT
3
D
10
/
STOPC
R0
1
/INT
2
R2
0
/EVND
INT
2
detection edge selection
Not used
R1
3
/
EVNB
*
3
*
6
*
4
32-kHz oscillation stop
*
5
Port D
3
DCR
Port D
7
DCR
Not used
Port D
2
DCR
Port D
6
DCR
Not used
Port D
1
DCR
Port D
5
DCR
Not used
Port D
0
DCR
Port D
4
DCR
Port D
8
DCR
Port R0
3
DCR
Port R1
3
DCR
Port R2
3
DCR
Port R3
3
DCR
Port R0
2
DCR
Port R1
2
DCR
Port R2
2
DCR
Port R3
2
DCR
Port R0
1
DCR
Port R1
1
DCR
Port R2
1
DCR
Port R3
1
DCR
Port R0
0
DCR
Port R1
0
DCR
Port R2
0
DCR
Port R3
0
DCR
Port R6
3
DCR
Port R7
3
DCR
Port R6
2
DCR
Port R7
2
DCR
Port R6
1
DCR
Port R7
1
DCR
Port R6
0
DCR
Port R7
0
DCR
Bank selection
Auto reload
on/off
Input capture
selection
Timer B register (lower digit)
Interrupt frame period selection
Clock source selection (timer C)
Timer C register (lower digit)
Timer C register (upper digit)
Clock source selection (timer D)
Timer D register (lower digit)
Timer D register (upper digit)
Not used
Timer B output mode selection
Timer D output mode selection
LCD input clock source selection
Register flag area
INT
3
detection edge selection
EVND detection edge selection
Not used
D
11
/
INT
0
R0
0
/
INT
1
4.
5.
6.
Transmit clock source selection
32-kHz oscillation division ratio
System oscillation frequency selection
1.
2.
3.
LCD display division resistor switch
Display on/off in watch mode
SO output level control in idle states
Notes:
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Figure 5 Special Function Register Area
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