參數(shù)資料
型號: HD4074629
廠商: Hitachi,Ltd.
英文描述: AS Microcomputer Incorporating a DTMF Generator Circuit(微計算機帶雙音多頻發(fā)生器電路)
中文描述: 由于微機安裝有雙音多頻發(fā)電機斷路器(微計算機帶雙音多頻發(fā)生器電路)
文件頁數(shù): 24/155頁
文件大小: 549K
代理商: HD4074629
HD404629R Series
24
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Cuntrol Bit
INT
0
1
INT
1
1
Timer A
Timer B or
INT
2
1
Timer C or
INT
3
1
Timer D or
INT
4
1
A/D or
Serial
IE
IF0 .
IM0
IF1 .
IM1
IFTA .
IMTA
IFTB .
IMTB
+ IF2
.
IM2
IFTC .
IMTC
+ IF3
.
IM3
IFTD .
IMTD
+ IF4
.
IM4
IFAD .
IMAD
+ IFS
.
IMS
Note:
1
1
1
0
0
0
0
0
0
*
1
0
0
0
0
0
*
*
1
0
0
0
0
*
*
*
1
0
0
0
*
*
*
*
1
0
0
*
*
*
*
*
1
0
*
*
*
*
*
*
1
Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note:
*
*
Stacking
The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.
Figure 10 Interrupt Processing Sequence
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