HD404829R Series
89
Transmit Clock Error Detection (In External Clock Mode):
The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 73.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode
register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.
Serial interrupt request flag (IFS: $023, bit 2) set: If the state is changed from transfer to another by
writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register A write or STS instruction execution must be programmed to be executed after
confirming that the
SCK
pin is at 1, that is, after executing the input instruction to port R2.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
Serial Mode Register A (SMRA: $005)
Serial Mode Register B (SMRB: $028)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Miscellaneous Register (MIS: $00C)
Serial Mode Register A (SMRA: $005):
This register has the following functions (figure 74).
R2
1
/
SCK
pin function selection
Transfer clock selection
Prescaler division ratio selection
Serial interface initialization
Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to
the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is
performed during data transfer, the serial interrupt request flag (IFS: $023, bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.