HD404829R Series
35
Subactive Mode:
The OSC
1
and OSC
2
oscillator stops and the MCU operates with a clock generated by
the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because
the operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244
μ
s or 122
μ
s by setting bit 2 (SSR2) of the
system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the
value is changed in subactive mode, the MCU may malfunction.
When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame:
In watch and subactive modes,
φ
CLK
is applied to timer A and the
INT
0
I
circuit.
Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure
18).
In watch and subactive modes, the timer-A/
INT
0
interrupt is generated synchronously with the interrupt
frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the
INT
0
signal is input asynchronously with the interrupt
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.
t
RC
T
T
X
T
T:
t :
Interrupt frame length
Oscillation stabilization period
(During the transition
from watch mode to
active mode only)
Interrupt strobe
INT
0
Interrupt request
generation
Active mode
Watch mode
Active mode
Oscillation
stabilization period
If the time from the fall of the
INT
0
signal until the interrrupt is accepted
and active mode is entered and is designated Tx, then Tx will be in the
following range:
T + t
RC
≤
Tx
≤
2T + t
RC
Note:
Figure 17 Interrupt Frame