HD404618 Series
43
Timers
The MCU has two prescalers (S and W) and three timer/counters (A, B, and C). Figures 26, 27 and 28
show their diagrams.
Prescaler S:
Eleven-bit counter that inputs the system clock signal. After being initialized to $000 by
MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset and in
the stop and watch modes. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C
input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode
register B (TMB), timer mode register C (TMC), and the serial mode register (SMR), respectively.
Prescaler W:
Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output
can be selected as a timer A input clock by timer mode register A (TMA).
Timer A:
Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and
incremented at each clock input. If an input clock is applied to timer A after it has reached $FF, an
overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts
from $00.
Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It
can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is
driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is
controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software.
1/4
1/2
32.768-kHz
oscillator
System
clock
Prescaler W
(PSW)
Selector
Selector
Prescaler S (PSS)
S
I
Timer A interrupt
request flag
(IFTA)
Clock
Overflow
Timer
counter A
(TCA)
Timer mode
register A
(TMA)
3
2 f
SUB
1/2 t
subcyc
(t
subcyc
)
PER
2
÷
4
÷
8
÷
3
÷
1
÷
5
÷
1
÷
2
÷
2
÷
8
÷
1
÷
3
÷
f
SUB
Figure 26 Timer A Block Diagram