參數(shù)資料
型號: HD404618FS
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer
中文描述: 4位單片機
文件頁數(shù): 17/89頁
文件大?。?/td> 358K
代理商: HD404618FS
HD404618 Series
17
Interrupts
The MCU has six interrupt sources: two external signals (
INT
0
and
INT
1
), three timer/counters (timers A,
B, and C), and serial interface (serial).
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Servicing:
Locations $000 through $003 in RAM space are
reserved for interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
Figure 7 is a block diagram of the interrupt control circuit. Table 2 lists interrupt priorities and vector
addresses, and table 3 lists the interrupt processing conditions for the six interrupt sources.
An interrupt request occurs when the IF is set to 1 and IM to 0. If the IE is 1 at that point, the interrupt is
processed. A priority programmable logic array (PLA) generates the vector address assigned to that
interrupt source.
Figure 8 shows the interrupt processing sequence, and figure 9 shows an interrupt processing flowchart.
After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset
in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during
the second and third cycles, and the program jumps to the vector address to execute the instruction in the
third cycle.
Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
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