FN2952.2 March 7, 2006 (16) TE10 Enable Hold CL
參數(shù)資料
型號: HD3-6408-9Z
廠商: Intersil
文件頁數(shù): 9/11頁
文件大小: 0K
描述: IC ASMA ADT CMOS 1.25MHZ 24DIP
標準包裝: 90
類型: Manchester 編碼器/解碼器
應(yīng)用: 安全系統(tǒng)
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 24-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
7
FN2952.2
March 7, 2006
(16) TE10
Enable Hold
CL = 50pF
10
-
ns
(17) TE11
Sync Hold
CL = 50pF
95
-
ns
DECODER TIMING
(18) FDC
Decoder Clock Frequency
CL = 50pF
0
-
12
MHz
(19) TDCR
Decoder Clock Rise Time
CL = 50pF
-
8
ns
(20) TDCF
Decoder Clock Fall Time
CL = 50pF
-
8
ns
(21) FDD
Data Rate
CL = 50pF
0
-
1.0
MHz
(22) TDR
Decoder Reset Pulse Width
CL = 50pF
150
-
ns
(23) TDRS
Decoder Reset Setup Time
CL = 50pF
75
-
ns
(24) TDRH
Decoder Reset Hold Time
CL = 50pF
10
-
ns
(25) TMR
Master Reset Pulse Width
CL = 50pF
150
-
ns
(26) TD1
Bipolar Data Pulse Width
Note 2, CL = 50pF
TDC +10
-
ns
(27) TD2
Sync Transition Span
Note 2, CL = 50pF
-
18TDC
-ns
(28) TD3
One Zero Overlap
Note 2, CL = 50pF
-
TDC -10
ns
(29) TD4
Short Data Transition Span
Note 2, CL = 50pF
-
6TDC
-ns
(30) TD5
Long Data Transition Span
Note 2, CL = 50pF
-
12TDC
-ns
(31) TD6
Sync Delay (ON)
CL = 50pF
-20
-
110
ns
(32) TD7
Take Data Delay (ON)
CL = 50pF
0
-
110
ns
(33) TD8
Serial Data Out Delay
CL = 50pF
-
80
ns
(34) TD9
Sync Delay (OFF)
CL = 50pF
0
-
110
ns
(35) TD10
Take Data Delay (OFF)
CL = 50pF
0
-
110
ns
(36) TD11
Valid Word Delay
CL = 50pF
0
-
110
ns
NOTE:
2. TDC = Decoder Clock Period = 1/FDC. (These parameters are guaranteed but not 100% tested).
Capacitance
TA = +25°C
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CIN
Input Capacitance
FREQ = 1MHz, all measurements
are referenced to device GND
-15-
pF
CO
Output Capacitance
-
15
-
pF
AC Electrical Specifications
VCC = 5.0V ±10%, TA = -40°C to +85°C (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HD-6408
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