- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1995 > HD3-6408-9Z (Intersil)IC ASMA ADT CMOS 1.25MHZ 24DIP PDF資料下載
參數(shù)資料
| 型號(hào)： | HD3-6408-9Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ASMA ADT CMOS 1.25MHZ 24DIP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類(lèi)型： | Manchester 編碼器/解碼器 |
| 應(yīng)用： | 安全系統(tǒng) |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
4
FN2952.2
March 7, 2006
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SClock input. An
auxiliary divide by six counter is provided on chip which can
be utilized to produce the SClock by dividing the DClock.
The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of the
ESC, a high at SS input actuates a Command sync or a low
will produce a Data sync for that word (2). When the Encoder
is ready to accept data, the SD output will go high and
remain high for sixteen ESC periods (3) - (4).
During these sixteen periods the data should be clocked into
the SD Input with every high-to-low transition of the ESC (3)
- (4). After the sync and Manchester II encoded data are
transmitted through the BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that
word (5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe
gap. ENCODER ENABLE must go low by time (5) as shown
to prevent a consecutive word from being encoded. At any
time a low on OI will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To Abort the Encoder transmission a positive pulse must be
applied at MR. Any time after or during this pulse, a low-to-
high transition on SCI clears the internal counters and
initializes the Encoder for a new word.
1ST HALF
0
1
2
3
4
5
6
7
15
16
17
TIMING
19
18
3
21
0
10
11
12
13
14
15
32
1
0
11
12
13
14
15
P
2ND HALF
32
1
0
11
12
13
14
15
P
SYNC
4
5
2
3
1
SCI
ESC
EE
SS
SD
SDI
BOO
BZO
DON’T CARE
VALID
HD-6408
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI1-565AJD-5 | CONV D/A 12BIT 6.7MHZ 24-DIP |
| HI1171JCB-T | CONV D/A 8BIT 40MSPS HS 24-SOIC |
| HI1175JCB-T | CONV A/D 8BIT 20MSPS 24-SOIC |
| HI1178JCQ | CONV D/A 8BIT TRPL 40MHZ 48-PQFP |
| HI3-674AKN-5 | IC ADC 12BIT 67KSPS 28-SBDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD3-6409-2 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC |
| HD3-6409-9 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 MANCHESTER 1MHZ 20PDIP IND RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HD3-6409-9+ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Encoder/Decoder |
| HD3-6409-9Z | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL MANCHESTER 1MHZ 20PDIP IND RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HD3-6409C-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。