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參數(shù)資料
| 型號(hào)： | HD3-6408-9Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ASMA ADT CMOS 1.25MHZ 24DIP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | Manchester 編碼器/解碼器 |
| 應(yīng)用： | 安全系統(tǒng) |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
5
FN2952.2
March 7, 2006
Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DClock input. The
Manchester II coded data can be presented to the Decoder
in one of two ways. The BOI and BZI inputs will accept data
from a differential output comparator. The UDI input can only
accept noninverted Manchester II coded data (e.g. from
BOO of an Encoder through an inverter to UDI).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated by the
CDS output. If the sync character was a command, this
output will go high (2) and remain high for sixteen DSC
periods (3), otherwise it will remain low. The TD output will
go high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SDO.
The decoded data available at SDO is in a NRZ format. The
DSC is provided so that the decoded bits can be shifted into
an external register on every low-to-high transition of this
clock (2) - (3). Note that DECODER SHIFT CLOCK may
adjust its phase up until the time that TAKE DATA goes high.
After all sixteen decoded bits have been transmitted (3) the
data is checked for odd parity. A high on VW output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1).
At any time in the above sequence a high input on DR during
a low-to-high transition of DSC will abort transmission and
initialize the Decoder to start looking for a new sync character.
2ND HALF
1ST HALF
0
1
2
3
4
5
6
7
8
16
171819
SYNC
15
14
13
12
11
10
14
13
12
11
10
21
0P
21
0P
15
14
13
12
4
3
2
1
0
VW
SDO
CDS
BZI
BOI
DSC
TIMING
FROM PREVIOUS RECEPTION
UNDEFINED
2
1
3
4
HD-6408
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD3-6409-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HD3-6409-9 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 MANCHESTER 1MHZ 20PDIP IND RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HD3-6409-9+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| HD3-6409-9Z | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL MANCHESTER 1MHZ 20PDIP IND RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HD3-6409C-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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