參數(shù)資料
型號(hào): HCPL-0710
英文描述: 40 ns Propagation Delay,CMOS Optocoupler(40 ns 傳播延遲,CMOS耦合器)
中文描述: 40納秒的傳播延遲,光耦的CMOS(40納秒的傳播延遲,耦合器的CMOS)
文件頁數(shù): 7/16頁
文件大小: 304K
代理商: HCPL-0710
7
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage
Symbol Min.
V
ISO
Typ. Max. Units
Test Conditions
RH
50%,
t = 1 min.,
T
A
= 25
°
C
V
I-O
= 500 Vdc
Fig.
Note
8, 9,
10
0710
2500
Vrms
7710
3750
Resistance
(Input-Output)
Capacitance
(Input-Output)
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
R
I-O
10
12
8
C
I-O
0.6
pF
f = 1 MHz
C
I
θ
jci
3.0
145
160
140
135
11
°
C/W
Thermocouple
located at center
underside of
package
θ
jco
P
PD
150
mW
Notes:
1. The LED is ON when V
I
is low and OFF
when V
I
is high.
2. t
PHL
propagation delay is measured
from the 50% level on the falling edge
of the V
I
signal to the 50% level of the
falling edge of the V
O
signal. t
PLH
propagation delay is measured from
the 50% level on the rising edge of the
V
I
signal to the 50% level of the rising
edge of the V
O
signal.
3. Mimimum Pulse Width is the shortest
pulse width at which 10% maximum,
Pulse Width Distortion can be guaran-
teed. Maximum Data Rate is the
inverse of Minimum Pulse Width.
Operating the HCPL-x710 at data rates
above 12.5 MBd is possible provided
PWD and data dependent jitter
increases and relaxed noise margins
are tolerable within the application.
For instance, if the maximum
allowable variation of bit width is 30%,
the maximum data rate becomes 37.5
MBd. Please note that HCPL-x710
performances above 12.5 MBd are not
guaranteed by Hewlett-Packard.
4. PWD is defined as |t
PHL
- t
PLH
|.
%PWD (percent pulse width distortion)
is equal to the PWD divided by pulse
width.
5. t
PSK
is equal to the magnitude of the
worst case difference in t
and/or
t
PLH
that will be seen between units at
any given temperature within the
recommended operating conditions.
6. CM
H
is the maximum common mode
voltage slew rate that can be sustained
while maintaining V
> 0.8 V
. CM
is the maximum common mode voltage
slew rate that can be sustained while
maintaining V
< 0.8 V. The common
mode voltage slew rates apply to both
rising and falling common mode
voltage edges.
7. Unloaded dynamic power dissipation is
calculated as follows: C
* V
DD2
* f +
I
* V
, where f is switching
frequency in MHz.
8. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
9. In accordance with UL1577, each
HCPL-0710 is proof tested by applying
an insulation test voltage
3000 V
RMS
for 1 second (leakage detection
current limit, I
I-O
5
μ
A). Each HCPL-
7710 is proof tested by applying an
insulation test voltage
4500 V rms
for 1 second (leakage detection
current limit, I
5
μ
A).
10. The Input-Output Momentary With-
stand Voltage is a dielectric voltage
rating that should not be interpreted as
an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or HP Application
Note 1074 entitled “Optocoupler
Input-Output Endurance Voltage.”
11. C
is the capacitance measured at pin
2 (V
I
).
Figure 1. Typical Output Voltage vs.
Input Voltage.
Figure 2. Typical Input Voltage
Switching Threshold vs. Input Supply
Voltage.
Figure 3. Typical Propagation Delays
vs. Temperature.
V
O
0
0
V
I
(V)
5
4
1
4
1
2
3
5
3
2
0 °C
25 °C
85 °C
V
I
4.5
1.6
V
DD1
(V)
5.5
2.1
1.7
5.25
4.75
5
2.2
2.0
1.8
1.9
0 °C
25 °C
85 °C
T
P
,
P
(
0
15
T
A
(C)
80
27
17
60
20
30
29
25
19
21
10
40
50
70
23
T
PLH
T
PHL
-7710
-0710
-7710
-0710
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