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參數(shù)資料
| 型號： | HCD40C4084 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip A/D Converter(帶片上A/D轉(zhuǎn)換器的低壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片的A / D轉(zhuǎn)換器（帶片上的A / D轉(zhuǎn)換器的低壓微計算機） |
| 文件頁數(shù)： | 35/162頁 |
| 文件大小： | 482K |
| 代理商： | HCD40C4084 |
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
35
Interrupts
There are a total of seven interrupt sources, comprising wakeup input (
WU
0
), external interrupts (
INT
0
),
timer/counter (timer A, timer B, timer C) interrupts, a serial interface interrupt, and an A/D converter
interrupt.
Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for
storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control
interrupts as a whole.
Of the interrupt sources, the A/D converter and serial interface share the same vector address. Software
must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt
handling.
Interrupt control bits and interrupt handling:
The interrupt control bits are mapped onto RAM addresses $000 to $003 and $023, and can be accessed by
RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software.
When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0,
and the interrupt masks (IM) are initialized to 1.
Figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector
addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of
interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an
interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The
vector address corresponding to the interrupt source is generated by the priority control circuit.
The interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10.
When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the
second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry
flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the
vector address and instruction execution is resumed from that address.
In each vector address area, a JMPL instruction should be written that branches to the start address of the
interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be
reset by software.
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