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| 型號(hào)： | HC05J5GRS |
| 英文描述： | 68HC05J5 General Release Specification |
| 中文描述： | 68HC05J5一般版本規(guī)范 |
| 文件頁數(shù)： | 33/106頁 |
| 文件大小： | 1366K |
| 代理商： | HC05J5GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INTERRUPTS
MOTOROLA
4-7
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the output of the logic OR function with the PA0 thru PA3 pins. The state of
the individual Port A pins can be checked by reading the appropriate Port A pins
as inputs.
NOTE
If enabled, the PA0 thru PA3 and PA7 pins will cause an IRQ interrupt regardless
of whether these pins are configured as inputs or outputs.
4.5.3 TIMER INTERRUPT (MFT)
The TIMER interrupt is generated by the multi-function timer when either a timer
overflow or a real time interrupt has occurred as described in
Section 8
. The inter-
rupt flags and enable bits for the Timer interrupts are located in the Timer Control
& Status Register (TCSR) located at $0008. The I-bit in the CCR must be clear in
order for the TIMER interrupt to be enabled. Either of these two interrupts will vec-
tor to the same interrupt service routine located at the address specified by the
contents of memory locations $0FF8 and $0FF9.
4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)
The Timer1 interrupt is generated by the 16-bit Timer when either a timer1 over-
flow or a input capture has occurred as described in
Section 9
. The interrupt flags
and enable bits for the Timer1 interrupt are located in the Timer1 Control & Status
Register (T1CR & T1SR) located at $0012, $0013. The I-bit in the CCR must be
cleared in order to enable the Timer1. Either of these two interrupts will vector to
the same interrupt service routine located at the address specified by the contents
of memory locations $0FF6 and $0FF7.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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