MOTOROLA
B-4
MC68HC05X16
Rev. 1
MC68HC705X32
15
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page
B-1.
Table B-1
Register outline
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on
reset
Undefined
Undefined
Undefined
Undefined
0000 0000
0000 0000
0000 0000
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
Mscellaneous
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
Options (OPTR)
(3)
Mask option register (MOR)
(4)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009 COCO ADRC ADON
PC2/ECLK
PD2
PD7
PD6
PD5
PD4
PD3
PD1
PD0
WOIE
CAF
E6LAT E6PGM ECLK
E1ERA E1LAT E1PGM 0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0
CH3
CH2
CH1
CH0
$000C POR
(1)
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
$7FDE
INTP
SPC0
T8
TCIE
TC
INTN
SCT1
INTE
SCT0
M
ILIE
IDLE
SFA
SCT0
WAKE
TE
OR
SFB
SCR2
CPOL
RE
NF
SM WDOG
(2)
u001 000u
SCR1
SCR0
CPHA
LBCL
RWU
SBK
FE
SPC1
R8
TIE
TDRE
00uu uuuu
Undefined
0000 0000
1100 000u
0000 0000
RIE
RDRF
ICIE
ICF1
OCIE
OCF1
TOIE
TOF
FOLV2 FOLV1
ICF2
OLV2
IEDG1 OLVL1 0000 00u0
OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
Not affected
EE1P
PBPD
SEC
PCPD Not affected
WOI
DIV2
DIV8
RTIM RWAT
WWAT