Rev. 3.00, 03/04, page xxxii of xl
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI.................................................639
Figure 20.8 Overview of Boot Mode State Transition Diagram.................................................641
Figure 20.9 Programming/Erasing Overview Flow....................................................................642
Figure 20.10 RAM Map When Programming/Erasing is Executed ...........................................643
Figure 20.11 Programming Procedure........................................................................................644
Figure 20.12 Erasing Procedure .................................................................................................649
Figure 20.13 Repeating Procedure of Erasing and Programming...............................................651
Figure 20.14 Procedure for Programming User MAT in User Boot Mode................................653
Figure 20.15 Procedure for Erasing User MAT in User Boot Mode..........................................654
Figure 20.16 Transitions to Error-Protection State.....................................................................667
Figure 20.17 Switching between the User MAT and User Boot MAT ......................................668
Figure 20.18 Memory Map in Programmer Mode......................................................................669
Figure 20.19 Boot Program States..............................................................................................671
Figure 20.20 Bit-Rate-Adjustment Sequence.............................................................................672
Figure 20.21 Communication Protocol Format..........................................................................673
Figure 20.22 New Bit-Rate Selection Sequence.........................................................................683
Figure 20.23 Programming Sequence.........................................................................................686
Figure 20.24 Erasure Sequence ..................................................................................................689
Section 21
Boundary Scan (JTAG)
Figure 21.1 JTAG Block Diagram..............................................................................................698
Figure 21.2 TAP Controller State Transitions............................................................................714
Figure 21.3 Reset Signal Circuit Without Reset Signal Interference..........................................718
Figure 21.4 Serial Data Input/Output (1)....................................................................................719
Figure 21.5 Serial Data Input/Output (2)....................................................................................720
Section 22
Clock Pulse Generator
Figure 22.1 Block Diagram of Clock Pulse Generator...............................................................721
Figure 22.2 Typical Connection to Crystal Resonator................................................................722
Figure 22.3 Equivalent Circuit of Crystal Resonator..................................................................722
Figure 22.4 Example of External Clock Input............................................................................723
Figure 22.5 Note on Board Design of Oscillation Circuit Section ..............................................725
Section 23
Power-Down Modes
Figure 23.1 Mode Transition Diagram.......................................................................................736
Figure 23.2 Medium-Speed Mode Timing.................................................................................740
Figure 23.3 Software Standby Mode Application Example.......................................................742
Figure 23.4 Hardware Standby Mode Timing............................................................................743
Section 25
Electrical Characteristics
Figure 25.1 Darlington Transistor Drive Circuit (Example).......................................................787
Figure 25.2 LED Drive Circuit (Example).................................................................................787
Figure 25.3 Output Load Circuit ................................................................................................788
Figure 25.4 System Clock Timing..............................................................................................789
Figure 25.5 Oscillation Stabilization Timing..............................................................................790