Rev. 3.00, 03/04, page xii of xl
Section 7 Data Transfer Controller (DTC)........................................................149
7.1
Features.............................................................................................................................149
7.2
Register Descriptions........................................................................................................151
7.2.1
DTC Mode Register A (MRA)............................................................................152
7.2.2
DTC Mode Register B (MRB).............................................................................153
7.2.3
DTC Source Address Register (SAR)..................................................................153
7.2.4
DTC Destination Address Register (DAR)..........................................................153
7.2.5
DTC Transfer Count Register A (CRA)..............................................................154
7.2.6
DTC Transfer Count Register B (CRB)...............................................................154
7.2.7
DTC Enable Registers (DTCER).........................................................................154
7.2.8
DTC Vector Register (DTVECR)........................................................................155
7.2.9
Keyboard Comparator Control Register (KBCOMP)..........................................156
7.2.10
Event Counter Control Register (ECCR).............................................................157
7.2.11
Event Counter Status Register (ECS)..................................................................158
7.3
DTC Event Counter..........................................................................................................159
7.3.1
Event Counter Handling Priority.........................................................................160
7.3.2
Usage Notes.........................................................................................................161
7.4
Activation Sources............................................................................................................161
7.5
Location of Register Information and DTC Vector Table................................................162
7.6
Operation ..........................................................................................................................165
7.6.1
Normal Mode.......................................................................................................166
7.6.2
Repeat Mode........................................................................................................167
7.6.3
Block Transfer Mode...........................................................................................168
7.6.4
Chain Transfer.....................................................................................................169
7.6.5
Interrupt Sources..................................................................................................170
7.6.6
Operation Timing.................................................................................................170
7.6.7
Number of DTC Execution States .......................................................................171
7.7
Procedures for Using DTC................................................................................................173
7.7.1
Activation by Interrupt.........................................................................................173
7.7.2
Activation by Software........................................................................................173
7.8
Examples of Use of the DTC............................................................................................174
7.8.1
Normal Mode.......................................................................................................174
7.8.2
Software Activation.............................................................................................174
7.9
Usage Notes......................................................................................................................176
7.9.1
Module Stop Mode Setting..................................................................................176
7.9.2
On-Chip RAM.....................................................................................................176
7.9.3
DTCE Bit Setting.................................................................................................176
7.9.4
Setting Required on Entering Subactive Mode or Watch Mode..........................176
7.9.5
DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .................176