Rev. 3.00, 03/04, page xvii of xl
12.9
Usage Notes......................................................................................................................330
12.9.1
Conflict between TCNT Write and Counter Clear...............................................330
12.9.2
Conflict between TCNT Write and Increment.....................................................331
12.9.3
Conflict between TCOR Write and Compare-Match...........................................332
12.9.4
Conflict between Compare-Matches A and B .....................................................333
12.9.5
Switching of Internal Clocks and TCNT Operation.............................................333
12.9.6
Mode Setting with Cascaded Connection............................................................335
Section 13 Watchdog Timer (WDT)..................................................................337
13.1
Features.............................................................................................................................337
13.2
Input/Output Pins..............................................................................................................339
13.3
Register Descriptions........................................................................................................340
13.3.1
Timer Counter (TCNT)........................................................................................340
13.3.2
Timer Control/Status Register (TCSR)................................................................340
13.4
Operation ..........................................................................................................................344
13.4.1
Watchdog Timer Mode........................................................................................344
13.4.2
Interval Timer Mode............................................................................................345
13.4.3
RESO
Signal Output Timing...............................................................................346
13.5
Interrupt Sources...............................................................................................................347
13.6
Usage Notes......................................................................................................................348
13.6.1
Notes on Register Access.....................................................................................348
13.6.2
Conflict between Timer Counter (TCNT) Write and Increment..........................349
13.6.3
Changing Values of CKS2 to CKS0 Bits.............................................................349
13.6.4
Changing Value of PSS Bit..................................................................................349
13.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode................350
13.6.6
System Reset by
RESO
Signal ............................................................................350
Section 14 Serial Communication Interface (SCI, IrDA, and CRC)................351
14.1
Features.............................................................................................................................351
14.2
Input/Output Pins..............................................................................................................355
14.3
Register Descriptions........................................................................................................356
14.3.1
Receive Shift Register (RSR) ..............................................................................356
14.3.2
Receive Data Register (RDR)..............................................................................356
14.3.3
Transmit Data Register (TDR).............................................................................357
14.3.4
Transmit Shift Register (TSR).............................................................................357
14.3.5
Serial Mode Register (SMR) ...............................................................................357
14.3.6
Serial Control Register (SCR) .............................................................................361
14.3.7
Serial Status Register (SSR) ................................................................................364
14.3.8
Smart Card Mode Register (SCMR)....................................................................368
14.3.9
Bit Rate Register (BRR)......................................................................................369
14.3.10
Serial Interface Control Register (SCICR) ..........................................................375
14.3.11
Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2)....................376
14.4
Operation in Asynchronous Mode....................................................................................380