866
HICR1—Host Interface Control Register 1
H'FE41
HIF (LPC)
7
LPCBSY
0
R
—
6
CLKREQ
0
R
—
5
IRQBSY
0
R
—
4
LRSTB
0
R/W
—
3
SDWNB
0
R/W
—
0
LSCIB
0
R/W
—
2
PMEB
0
R/W
—
1
LSMIB
0
R/W
—
Bit
Initial value
Slave Read/Write
Host Read/Write
LSCI output bit
HICR0
Bit 0
LSCIE
0
HICR1
Bit 0
LSCIB
0
1
0
1
Description
LSCI output disabled, other function of pin enabled
LSCI output disabled, other function of pin enabled
LSCI output enabled, LSCI pin output goes to 0 level
LSCI output enabled, LSCI pin output is high-impedance
1
LSMI output bit
HICR0
Bit 1
LSMIE
0
HICR1
Bit 1
LSMIB
0
1
0
1
Description
LSMI output disabled, other function of pin enabled
LSMI output disabled, other function of pin enabled
LSMI output enabled,
LSMI
pin output goes to 0 level
LSMI output enabled,
LSMI
pin output is high-impedance
1
PME output bit
HICR0
Bit 2
PMEE
0
HICR1
Bit 2
PMEB
0
1
0
1
Description
PME output disabled, other function of pin enabled
PME output disabled, other function of pin enabled
PME output enabled,
PME
pin output goes to 0 level
PME output enabled,
PME
pin output is high-impedance
1
LPC software shutdown bit
0
Normal state
[Clearing conditions]
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown
(falling edge of
signal when SDWNE = 1)
LPC hardware shutdown release
(rising edge of
signal when SDWNE = 0)
LPC software shutdown state
[Setting condition]
Writing 1 after reading SDWNB = 0
LPC software reset bit
0
Normal state
[Clearing conditions]
Writing 0
LPC hardware reset
1
LPC software reset state
[Setting condition]
Writing 1 after reading LRSTB = 0
SERIRQ busy
0
SERIRQ transfer frame wait state
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
End of SERIRQ transfer frame
1
SERIRQ transfer processing in progress
[Setting condition]
Start of SERIRQ transfer frame
1
LCLK request
0
No LCLK restart request
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
SERIRQ is set to continuous mode
There are no further interrupts for transfer to the host in quiet mode
LCLK restart request issued
[Setting condition]
In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped
1
LPC busy
0
Host interface is in transfer cycle wait state
Bus idle, or transfer cycle not subject to processing is in progress
Cycle type or address indeterminate during transfer cycle
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
Forced termination (abort) of transfer cycle subject to processing
Normal termination of transfer cycle subject to processing
Host interface is performing transfer cycle processing
[Setting condition]
Match of cycle type and address
1