iii
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions......................................................................................................... 101
5.2.1
System Control Register (SYSCR)...................................................................... 101
5.2.2
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 102
5.2.3
IRQ Enable Register (IER) .................................................................................. 103
5.2.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 103
5.2.5
IRQ Status Register (ISR).................................................................................... 104
5.2.6
Keyboard Matrix Interrupt Mask Register (KMIMR).......................................... 105
5.2.7
Keyboard Matrix Interrupt Mask Register A (KMIMRA) Wakeup Event
Interrupt Mask Registr B (WUEMRB)................................................................ 106
5.2.8
Address Break Control Register (ABRKCR)....................................................... 109
5.2.9
Break Address Registers A, B, C (BARA, BARB, BARC)................................. 110
Interrupt Sources................................................................................................................ 111
5.3.1
External Interrupts................................................................................................ 111
5.3.2
Internal Interrupts................................................................................................. 113
5.3.3
Interrupt Exception Vector Table......................................................................... 113
Address Breaks.................................................................................................................. 116
5.4.1
Features ................................................................................................................ 116
5.4.2
Block Diagram...................................................................................................... 116
5.4.3
Operation.............................................................................................................. 117
5.4.4
Usage Notes.......................................................................................................... 117
Interrupt Operation............................................................................................................ 119
5.5.1
Interrupt Control Modes and Interrupt Operation................................................ 119
5.5.2
Interrupt Control Mode 0...................................................................................... 122
5.5.3
Interrupt Control Mode 1...................................................................................... 124
5.5.4
Interrupt Exception Handling Sequence .............................................................. 127
5.5.5
Interrupt Response Times..................................................................................... 129
Usage Notes....................................................................................................................... 130
5.6.1
Contention between Interrupt Generation and Disabling..................................... 130
5.6.2
Instructions that Disable Interrupts...................................................................... 131
5.6.3
Interrupts during Execution of EEPMOV Instruction.......................................... 131
DTC Activation by Interrupt ............................................................................................. 132
5.7.1
Overview.............................................................................................................. 132
5.7.2
Block Diagram...................................................................................................... 132
5.7.3
Operation.............................................................................................................. 133
Features ................................................................................................................
Block Diagram......................................................................................................
Pin Configuration .................................................................................................
Register Configuration ......................................................................................... 100
97
98
99
5.2
5.3
5.4
5.5
5.6
5.7
Section 6
6.1
Bus Controller
.................................................................................................. 135
Overview............................................................................................................................ 135
6.1.1
Features ................................................................................................................ 135
6.1.2
Block Diagram...................................................................................................... 136