Rev. 2.0, 08/02, page ix of xxxviii
5.3.7
Wake-Up Event Interrupt Mask Register (WUEMRB)........................................92
Interrupt Sources...............................................................................................................94
5.4.1
External Interrupts................................................................................................94
5.4.2
Internal Interrupts.................................................................................................96
Interrupt Exception Handling Vector Table......................................................................96
Interrupt Control Modes and Interrupt Operation .............................................................99
5.6.1
Interrupt Control Mode 0 .....................................................................................99
5.6.2
Interrupt Control Mode 1 .....................................................................................101
5.6.3
Interrupt Exception Handling Sequence...............................................................103
5.6.4
Interrupt Response Times.....................................................................................105
5.6.5
DTC Activation by Interrupt................................................................................106
Address Break...................................................................................................................107
5.7.1
Features................................................................................................................107
5.7.2
Block Diagram.....................................................................................................108
5.7.3
Operation..............................................................................................................108
5.7.4
Usage Notes..........................................................................................................109
Usage Notes.......................................................................................................................111
5.8.1
Conflict between Interrupt Generation and Disabling..........................................111
5.8.2
Instructions that Disable Interrupts ......................................................................111
5.8.3
Interrupts during Execution of EEPMOV Instruction..........................................112
5.8.4
Setting on Product Incorporating DTC.................................................................112
5.8.5
IRQ Status Register (ISR)....................................................................................112
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
5.4
5.5
5.6
5.7
5.8
Section 6 Bus Controller....................................................................................113
6.1
Features .............................................................................................................................113
6.2
Input/Output Pins ..............................................................................................................114
6.3
Register Descriptions.........................................................................................................114
6.3.1
Bus Control Register (BCR).................................................................................115
6.3.2
Wait State Control Register (WSCR)...................................................................116
6.4
Bus Control .......................................................................................................................117
6.4.1
Bus Specifications................................................................................................117
6.4.2
Advanced Mode...................................................................................................118
6.4.3
Normal Mode.......................................................................................................118
6.4.4
I/O Select Signals.................................................................................................119
6.5
Basic Bus Interface............................................................................................................120
6.5.1
Data Size and Data Alignment.............................................................................120
6.5.2
Valid Strobes........................................................................................................121
6.5.3
Basic Operation Timing.......................................................................................122
6.5.4
Wait Control.........................................................................................................130
6.6
Burst ROM Interface.........................................................................................................131
6.6.1
Basic Operation Timing.......................................................................................131
6.6.2
Wait Control.........................................................................................................132