Rev. 2.0, 08/02, page viii of xxxviii
2.8
2.9
Processing States...............................................................................................................58
Usage Notes.......................................................................................................................60
2.9.1
Note on TAS Instruction Usage...........................................................................60
2.9.2
Note on STM/LDM Instruction Usage.................................................................60
2.9.3
Note on Bit Manipulation Instructions.................................................................60
2.9.4
EEPMOV Instruction...........................................................................................62
Section 3 MCU Operating Modes.....................................................................63
3.1
MCU Operating Mode Selection.......................................................................................63
3.2
Register Descriptions ........................................................................................................63
3.2.1
Mode Control Register (MDCR)..........................................................................64
3.2.2
System Control Register (SYSCR) ......................................................................65
3.2.3
Serial Timer Control Register (STCR).................................................................67
3.3
Operating Mode Descriptions ...........................................................................................69
3.3.1
Mode 1.................................................................................................................69
3.3.2
Mode 2.................................................................................................................69
3.3.3
Mode 3.................................................................................................................69
3.3.4
Pin Functions in Each Operating Mode ...............................................................69
3.4
Address Map in Each Operating Mode.............................................................................71
Section 4 Exception Handling...........................................................................79
4.1
Exception Handling Types and Priority............................................................................79
4.2
Exception Sources and Exception Vector Table ...............................................................80
4.3
Reset..................................................................................................................................81
4.3.1
Reset Exception Handling....................................................................................81
4.3.2
Interrupts after Reset............................................................................................82
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled.........................................82
4.4
Interrupt Exception Handling............................................................................................82
4.5
Trap Instruction Exception Handling................................................................................82
4.6
Stack Status after Exception Handling..............................................................................83
4.7
Usage Note........................................................................................................................84
Section 5 Interrupt Controller ...........................................................................85
5.1
Features.............................................................................................................................85
5.2
Input/Output Pins ..............................................................................................................87
5.3
Register Descriptions ........................................................................................................87
5.3.1
Interrupt Control Registers A to C (ICRA to ICRC)............................................88
5.3.2
Address Break Control Register (ABRKCR).......................................................89
5.3.3
Break Address Registers A to C (BARA to BARC)............................................89
5.3.4
IRQ Sense Control Registers (ISCRH, ISCRL)...................................................90
5.3.5
IRQ Enable Register (IER) ..................................................................................91
5.3.6
IRQ Status Register (ISR)....................................................................................92