參數(shù)資料
型號(hào)： GS8662Q18BGD-357IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 850K
代理商： GS8662Q18BGD-357IT
GS8662Q08/09/18/36BD-357/333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
9/36
2011, GSI Technology
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 ns to reset the DLL after the
clocks become stablized.
DLL Constraints
The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar in AC Characteristics
table).
The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired
operating clock frequency.
If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 2048 cycles is required for DLL lock.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
相關(guān)PDF資料
PDF描述
GS8662Q18GE-167IT 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165
GS8662R09BD-350 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
GS8662R09BGD-400I 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
GS88037BT-225I 256K X 36 CACHE SRAM, 2.5 ns, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662Q18E-167 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q18E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q18E-200 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
GS8662Q18E-200I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
GS8662Q18E-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
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