參數(shù)資料
型號(hào): GS8641E18F-200IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 4M X 18 CACHE SRAM, 7.5 ns, PBGA165
封裝: 1 MM PITCH, BGA-165
文件頁數(shù): 15/31頁
文件大小: 769K
代理商: GS8641E18F-200IT
GS8641E18/32/36F-300/250/200/167
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 3/2005
22/31
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence
Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X X X X
0
00
X
100
1000010
00
0
0 0 1 1 0 1 1 0 0 1
1
x18
X X X X
0
00
X
100
1000010
10
0
0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
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參數(shù)描述
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GS8641E32GF-167 制造商:GSI Technology 功能描述:2MBX32,DCD PIPELINE/FLOWTHROUGH,PB-FREE,165 BGA,300MHZ,5.5NS - Trays
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