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參數(shù)資料
| 型號： | GS84118AT-133IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE TAG SRAM, 11 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 404K |
| 代理商： | GS84118AT-133IT |
GS84118AT/B-166/150/130/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 4/2005
4/20
2001, GSI Technology
Pin Description
Symbol
Description
An
Address Input Signals
CLK
Clock Input Signal
BWE
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
BW1
Byte Write signal for data outputs 1 thru 8
BW2
Byte Write signal for data outputs 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
Chip Enables
OE
Output Enable
ADV
Burst address advance
ADSP, ADSC
Address status signals
DQ1–DQ16
Data Input and Output pins
DQP1–DQP2
Parity Input and Output pins
MATCH
Match Output
MOE
Match Output Enable
DE
Data Enable—Data input registers are updated only when DE is active.
ZZ
Power down control—Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
LBO
Linear Order Burst mode
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
TCK
Test Clock
VDD
3.3 V power supply
VSS
Ground
VDDQ
2.5 V/3.3 V output power supply
NC
No Connect
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS84118AT-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118AT-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118AT-166 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118AT-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118B-100 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
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