參數(shù)資料
型號(hào): GS84118AB-166IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 18 CACHE TAG SRAM, 8.5 ns, PBGA119
封裝: FBGA-119
文件頁(yè)數(shù): 4/20頁(yè)
文件大?。?/td> 404K
代理商: GS84118AB-166IT
GS84118AT/B-166/150/130/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 4/2005
12/20
2001, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-166
-150
-133
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
6.0
6.7
7.5
10
ns
Clock to Output Valid
tKQ
3.5
3.8
4
4.5
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ1
1.5
1.5
1.5
1.5
ns
Clock to Match Valid
tKM
3.5
3.8
4
4.5
ns
Clock to Match Invalid
tKMX
1.5
1.5
1.5
1.5
ns
Clock to Match in Low-Z
tMLZ1
1.5
1.5
1.5
1.5
ns
Flow
Through
Clock Cycle Time
tKC
10.0
10.0
15.0
15.0
ns
Clock to Output Valid
tKQ
8.5
10.0
11.0
12.0
ns
Clock to Output Invalid
tKQX
3.0
3.0
3.0
3.0
ns
Clock to Output in Low-Z
tLZ1
3.0
3.0
3.0
3.0
ns
Clock to Match Valid
tKM
8.5
10.0
11.0
12.0
ns
Clock to Match Invalid
tKMX
3.0
3.0
3.0
3.0
ns
Clock to Match in Low-Z
tMLZ1
3.0
3.0
3.0
3.0
ns
Clock HIGH Time
tKH
1.3
1.5
1.7
2
ns
Clock LOW Time
tKL
1.5
1.7
1.9
2.2
ns
Clock to Output in High-Z
tHZ1
1.5
3.5
1.5
3.8
1.5
4
1.5
5
ns
OE to Output Valid
tOE
3.5
3.8
4
5
ns
OE to output in Low-Z
tOLZ1
0—0—0—0—
ns
OE to output in High-Z
tOHZ1
—3.5
—3.8
4
5
ns
MOE to Match Valid
tMOE
3.5
3.8
4
5
ns
MOE to Match in Low-Z
tMOLZ1
0—0—0—0—
ns
MOE to Match in High-Z
tMOHZ1
—3.5
—3.8
4
5
ns
Setup time
tS
1.5
1.5
2.0
2.0
ns
Hold time
tH
0.5
0.5
0.5
0.5
ns
ZZ setup time
tZZS2
5—5—5—5—
ns
ZZ hold time
tZZH2
1—1—1—1—
ns
ZZ recovery
tZZR
20
20
20
20
ns
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