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參數(shù)資料
| 型號： | GS840H18AT-100T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 12 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 1176K |
| 代理商： | GS840H18AT-100T |
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Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS840H18/32/36AT/B-180/166/150/100
Rev: 1.12 4/2007
11/31
1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
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| GS840H18AT-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
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| GS840H18AT-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
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