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參數(shù)資料
| 型號： | GS84018AB-190 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 7.5 ns, PBGA119 |
| 封裝： | FPBGA-119 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 1248K |
| 代理商： | GS84018AB-190 |
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Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS84018/32/36AT/B-190/180/166/150/100
Rev: 1.18 3/2007
11/31
1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS84018AGB-100 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 256KX18 12NS/4.5NS 119FBGA - Trays |
| GS84018AGB-100I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 256KX18 12NS/4.5NS 119FBGA - Trays |
| GS84018AGB-150 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 256KX18 10NS/3.8NS 119FBGA - Trays |
| GS84018AGB-150I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 256KX18 10NS/3.8NS 119FBGA - Trays |
| GS84018AGB-166 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 256KX18 8.5NS/3.5NS 119FBGA - Trays |
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