參數(shù)資料
型號(hào): GS832236B-225
廠商: GSI TECHNOLOGY
元件分類(lèi): SRAM
英文描述: 1M X 36 CACHE SRAM, 7 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, FBGA-119
文件頁(yè)數(shù): 22/46頁(yè)
文件大?。?/td> 1592K
代理商: GS832236B-225
GS832218(B/E)/GS832236(B/E)/GS832272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.07a 12/2007
29/46
2001, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents TBD for this part.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
相關(guān)PDF資料
PDF描述
GS832236E-225IV 1M X 36 CACHE SRAM, 7 ns, PBGA165
GS8322Z18E-225VT 2M X 18 ZBT SRAM, 7 ns, PBGA165
GS8322ZV72GC-150IT 512K X 72 ZBT SRAM, 8.5 ns, PBGA209
GS8322ZV36GB-200T 1M X 36 ZBT SRAM, 7.5 ns, PBGA119
GS8322ZV36GE-225IT 1M X 36 ZBT SRAM, 7 ns, PBGA165
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