參數(shù)資料
型號(hào)： GS8180D09
廠商： GSI TECHNOLOGY
英文描述： 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述： 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM）
文件頁數(shù)： 11/33頁
文件大?。?/td> 874K
代理商： GS8180D09
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
11/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
Special Functions
Echo Clock
Σ
RAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. Sigma RAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. Echo Clocks are always
active unless deselected by E2 or E3. The deselection of Echo Clock drivers is always pipelined to the same degree as output data.
Deselection of the RAM via E1 does not deactivate the Echo Clocks.
Programmable Enables
Σ
RAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V
DD
,
E2 functions as an active high enable. If EP2 is held to V
SS
, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four
Σ
RAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
Σ
RAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic
A
CK
E1
E2
E3
W
D
A
0
–A
n
CK
W
Q
0
–Q
n
D
0
–D
n
Bank 0
Bank 1
Bank 2
Bank 3
Bank Enable Truth Table
EP2
VSS
VSS
VDD
VDD
EP3
VSS
VDD
VSS
VDD
E2
E3
Bank 0
Bank 1
Bank 2
Bank 3
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
E1
A
n – 1
A
n
A
0
–A
n-2
A
n-1
A
n
A
0
- A
n-2
A
n-1
A
n
A
0
- A
n-2
A
n-1
A
n
A
0
- A
n-2
Q
A
CK
E2
E3
W
D
Q
A
CK
E2
E3
W
D
Q
A
CK
E2
E1
E3
W
D
Q
E1
E1
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