參數(shù)資料
型號(hào)： GS8162Z72CGC-250IVT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 256K X 72 ZBT SRAM, 5.5 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-209
文件頁(yè)數(shù)： 11/27頁(yè)
文件大?。?/td> 727K
代理商： GS8162Z72CGC-250IVT
GS8162Z72CC-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 4/2008
19/27
2004, GSI Technology
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
M*
1
0
Control Signals
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
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