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參數(shù)資料
| 型號： | GS816032T-250T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 CACHE SRAM, 5.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 648K |
| 代理商： | GS816032T-250T |
GS816018/32/36T-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.14 11/2004
7/25
1999, GSI Technology
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS816036BGT-150 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 100TQFP - Trays |
| GS816036BGT-150I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 100TQFP - Trays |
| GS816036BGT-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 100TQFP - Trays |
| GS816036BGT-150T | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Tape and Reel |
| GS816036BGT-150V | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 100TQFP - Trays |
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