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參數(shù)資料
| 型號： | GMZAN3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 39/53頁 |
| 文件大?。?/td> | 556K |
| 代理商： | GMZAN3 |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
44
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
DATA
DEVICEADDRESS
DATA
START
ACK
OPERATIONCODE
START
HFS
HCLK
STOP
DEVICEADDRESS
REGISTERADDRESS
R/W ACK
ACK
Figure 28.
2-Wire Read Operation (0x9x and 0xAx)
Please note that in all the above operations the operation code includes two address bits, as described in
4.15.3 8-bit Parallel Interface
The 8-bit parallel interface connects to the external 8051 microcontroller’s external memory interface
utilizing the following signals: AD[7..0], ALE, WR#, RD#. An additional input signal (REG_MEM) is
used to distinguish between the register set and the OSD SRAM. When REG_MEM is held low the
gmZAN3 register set is selected and when it is held high the OSD SRAM will be active. The bus timing
bytes.
The ALE signal is used to latch the 8-bits of address on the microprocessor’s multiplexed Address/Data
bus.
AD[7..0]
RDn
ALE
WRn
MEM_REG
AD[7..0]
RDn
ALE
WRn
Output Port
MCU
ZAN3
Figure 29.
8-bit Parallel Interface
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