參數(shù)資料
型號(hào): GMS90L320
英文描述: 8-Bit Single-Chip Microcontrollers(低電壓,8位單片微控制器)
中文描述: 8位單芯片微控制器(低電壓,8位單片微控制器)
文件頁(yè)數(shù): 10/46頁(yè)
文件大?。?/td> 683K
代理商: GMS90L320
GMS90C320
6
OCT. 2000 Ver 1.2
Pin Definitions and functions
Symbol
Pin Number
Input/
Output
Function
P-LCC-44
P-DIP-40
P-MQFP-
44
P1.0-P1.7
2-9
1-8
40-44,
1-3
I/O
Port1
is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(I
IL
, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.
2
3
1
2
40
41
P1.0/T2: Timer/counter 2 external count input
P1.1/T2EX: Timer/counter 2 trigger input
P3.0-P3.7
11,13-
19
10-17
5, 7-
13
I/O
Port 3
is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (I
IL
, in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.
11
10
5
P3.0/RxD
receiver data input (asynchronous) or data input
output (synchronous) of the serial interface 0
13
11
7
P3.1 / TxD
transmitter data output (asynchronous) or clock
output (synchronous) of the serial interface 0
14
12
8
P3.2 / INT0
interrupt 0 input / timer 0 gate control
15
13
9
P3.3 / INT1
interrupt 1 input / timer 1 gate control
16
14
10
P3.4 / T0
counter 0 input
17
15
11
P3.5 / T1
counter 1 input
18
16
12
P3.6 / WR
the write control signal latches the data byte from
port 0 into the external data memory
19
17
13
P3.7 / RD
the read control signal enables the external data
memory to port 0
XTAL2
20
18
14
O
XTAL2
Output of the inverting oscillator amplifier
XTAL1
21
19
15
I
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no require-
ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divide-
by-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.
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