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| 型號(hào)： | GMS81C2120K |
| 廠(chǎng)商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁(yè)數(shù)： | 68/93頁(yè) |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C2120K |
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GMS81C1404/GMS81C1408
66
June. 2001 Ver 1.2
Release the STOP mode
The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues. If I-flag = 1, the normal interrupt response takes place.
If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine. (refer to Figure 19-1 )
By reset, exit from Stop mode is shown in Figure 19-3
.When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. Figure 19-2 shows the timing diagram. When release
the Stop mode, the Basic interval timer is activated on
wake-up. It is increased from 00
H
until FF
H
. The count
overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler di-
vide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized..
Figure 19-1 STOP Releasing Flow by Interrupts
Figure 19-2 Timing of STOP Mode Release by External Interrupt
IEXX
=0
=1
STOP
INSTRUCTION
STOP Mode
Interrupt Request
STOP Mode Release
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
=0
Master Interrupt
Enable Bit PSW[2]
Corresponding Interrupt
Enable Bit (IENH, IENL)
~
STOP Mode
Normal Operation
Oscillator
(X
IN
pin)
~
~
N+1
N
N+2
00
01
FE
FF
00
00
N-1
N-2
~
~
~
~
~
Clear Basic Interval Timer
STOP Instruction Execution
Normal Operation
Stabilizing Time
t
ST
> 20mS
Internal
Clock
External
Interrupt
BIT
Counter
~
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