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參數資料
| 型號： | GMS81C2120K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數： | 59/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C2120K |
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GMS81C1404/GMS81C1408
June. 2001 Ver 1.2
57
17. INTERRUPTS
The GMS81C1404 and GMS81C1408 interrupt circuits
consist of Interrupt enable register (IENH, IENL), Inter-
rupt request flags of IRQH, IRQL, Interrupt Edge Selec-
tion Register (IEDS), priority circuit and Master enable
flag(“I” flag of PSW). The configuration of interrupt cir-
cuit is shown in Figure 17-1 and Interrupt priority is shown
in Table 17-1 .
The External Interrupts INT0, INT1, INT2 and INT3 can
each be transition-activated (1-to-0, 0-to-1 and both transi-
tion).
The flags that actually generate these interrupts are bit
INT0IF, INT1IF, INT2IF and INT3IF in Register IRQH.
When an external interrupt is generated, the flag that gen-
erated it is cleared by the hardware when the service rou-
tine is vectored to only if the interrupt was transition-
activated.
The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are
generated by T0IF, T1IF, T2IF and T3IF, which are set by
a match in their respective timer/counter register. The AD
converter Interrupt is generated by ADIF which is set by
finishing the analog to digital conversion. The Watch dog
timer Interrupt is generated by WDTIF which set by a
match in Watch dog timer register (when the bit WDTON
is set to “0”). The Basic Interval Timer Interrupt is gener-
ated by BITIF which is set by a overflowing of the Basic
Interval Timer Register(BITR).
Figure 17-1 Block Diagram of Interrupt Function
BIT
BITIF
WDTIF
WDT
A/D Converter
Timer 1
Timer 0
External Int. 1
External Int. 0
IENH
Interrupt Enable
Register (Higher byte)
Interrupt Enable
Register (Lower byte)
IRQH
IRQL
Interrupt
Vector
Address
Generator
Internal bus line
Internal bus line
Release STOP
To CPU
Interrupt Master
Enable Flag
I Flag
IENL
P
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
INT0IF
INT1IF
T0IF
T1IF
ADIF
7
6
5
4
7
6
5
IEDS
Timer 3
Timer 2
External Int. 3
External Int. 2
INT2IF
INT3IF
T2IF
T3IF
3
2
1
0
IEDS
SPI
SPIF
5
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