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參數(shù)資料
| 型號： | GLT41116 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64k x 16 CMOS Dynamic RAM with Fast Page Mode |
| 中文描述： | 64k的× 16的CMOS動態(tài)隨機(jī)存儲器的快速頁面模式 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 106K |
| 代理商： | GLT41116 |
6
G-LINK Technology
GLT41116
July 1998 (Rev. 1)
1. An initial pause of 100
s is required after power-up followed by any 8 RAS only Refresh or CAS before RAS Refresh Cycles to initialize the internal circuit.
2. VIH (min) and VIL (min) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max), AC measurements as-
sume tT = 3 ns.
3. Measured with an equivalent to 2 TTL loads and 100 pF.
4. For read cycles, the access time is defined as follows:
tRAD (max.) and tRCD (max.) indicate the points which the access time changes and are not the limits of operation.
5. tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to VOH or VOL.
6. tCRP (min.) requirement should be applicable for RAS, CAS cycle preceded by any cycles.
7. Either tRCH (min.) or tRRH (min) must be satisfied for a read cycle.
8. tWP (min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH (min.) should be satisfied.
9. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS ≥ tWCS (min.), the cycle
is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD (min.), tRWD ≥ tRWD (min.) and tAWD ≥ tAWD (min.),
then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
10. This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write orr read modify write cycles.
11. tAR, tWCR, and tDHR are referenced to tRAD(max.).
Fast Page Mode Read Modify Write Cycle Time
tPRWC
48–60–53–65–
ns
CAS Precharge Time (Fast Page Mode)
tCP
6–6–7–7–
ns
RAS Pulse Width (Fast PAge Mode)
tRASP
30
100k
35
100k
40
100k
45
100k
ns
RAS Hold Time From CAS Precharge
tRHCP
25–25–25–30–
ns
Access Time From OE
tOEA
–10–11–12–12
ns
OE to Delay Time
tOED
8–8–8–8–
ns
Output Buffer Turn-off Delay Time From OE
tOEZ
3
–
383838
ns
[5]
OE Hold Time
tOEH
6–6–7–7–
ns
WE Hold Time (Hidden Refresh Cycle)
tWHR
15–15–15–15
ns
Refresh Time (256 Cycles)
tREF
–4–4–4–4
ms
AC Characteristics (0
°C ≤ T
A ≤ 70 °C, VCC = 5.0V ± 10%)
[1] [2]
Parameter
Symbol
-30
-35
-40
-45
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Input Conditions
Access Time
tRAD ≤ tRAD (max.) and tRCD ≤ tRCD (max.)
tRAC (Max.)
tRAD (max.) < tRAD and tRCD ≤ tRCD (max.)
tAA (Max.)
tRCD (max). < tRCD
tCAC (Max.)
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