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參數(shù)資料
| 型號(hào)： | GF9101 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Multirate Digital Filter |
| 中文描述： | 高性能多速率數(shù)字濾波器 |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 188K |
| 代理商： | GF9101 |
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G
PIPELINE_IN, PIPELINE_OUT STAGE
The calculated filter sum from the adder tree and delay
enters into the pipelined output stage. Figure 5 shows the
block diagram for the pipelined structure. FB_SEL
determines whether the sum is added to the current
PIPELINE_OUT or the registered PIPELINE_IN. The result is
then registered at PIPELINE_OUT. When using one GF9101,
this configuration can be used to add two partial filter sums
from the A and B registers. Another application would be to
use the PIPELINE_IN port for adding DC offset or SYNC
and BURST signals (i.e. for 4:2:2 to 4
SC
rate conversion).
This can be achieved by clocking in the SYNC and BURST
signals from an external PROM connected to the
PIPELINE_IN.
By connecting PIPELINE_OUT of one GF9101 device to
PIPELINE_IN of another, up to three GF9101
’
s may be
cascaded to form larger filters.
Fig. 5 Block Diagram for Pipelined Output Stage
Fig. 6 Timing Diagram for the Pipelined Output Stage
APPLICATION NOTES
Video applications for the GF9101 include video rate
conversion and high performance FIR filters. The following
section presents a number of examples which show odd
and even symmetric and asymmetric filters.
ODD-TAP SYMMETRIC FILTER
The GF9101 can be configured as an Odd-tap symmetric
filter. A 23-tap odd-symmetric filter using one GF9101 will
be discussed. For an odd-tap symmetric filter, the
configuration word is shown in Table 7.
The maximum data rate using this filter configuration is 20
MHz, where the filter is clocked at twice the data rate of 40
MHz, the frequency of CLK_IN. The filter has input data A
n
and filter data coefficients Cn (C0
—
> C11) as shown in
Figure 7. The input enters the filter at DATA_A_IN and exits
the filter from DATA_B_OUT. The coefficient C11 is only
multiplied by the data in reg. A_12 and reg.B_12 is
bypassed. The data is shifted into the register by clocking
ENA and ENB at the same time at half the CLK_IN
frequency. The filter timing is shown in Figure 8.
PIPELINE
–
OUT
1
0
20
PIPELINE
–
IN
FB
–
SEL
CLK
–
IN
20
20
20
GF9101
FILTER
–
SUM
PROM
R
R
R
+
X X X
X X X
FILTER_SUM
PIPELINE_IN
FB_SEL
CLK_IN
SUM 2
SUM 1
SUM 3
X X X
PIPELINE_OUT
003H
X X X
X X X
SUM 1
X X X
003
H
S+
S+
SUM 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GF9101-CMQ | High Performance Multirate Digital Filter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GF9101-CMQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Multirate Digital Filter |
| GF9102ACPM | 制造商:Gennum Corporation 功能描述: |
| GF9102ACTM | 制造商:Gennum Corporation 功能描述: |
| GF9103 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Over-Sampling Color Space Converter for Video Monitoring |
| GF9103-CPS | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Over-Sampling Color Space Converter for Video Monitoring |
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