參數(shù)資料
型號(hào): GF9101
廠商: Electronic Theatre Controls, Inc.
英文描述: High Performance Multirate Digital Filter
中文描述: 高性能多速率數(shù)字濾波器
文件頁數(shù): 12/23頁
文件大?。?/td> 188K
代理商: GF9101
520 - 64 - 7
12
G
Fig. 11 Timing Diagram for a 24 Tap Asymmetric Filter
Fig. 11a Data Flow Diagram for a 24 Tap Asymmetric Filter
Fig. 11b Data Flow Diagram for a 24 Tap Asymmetric Filter
CASCADING
In the previous section, configuration for a 24 tap filter using
only one GF9101 was shown. To realize higher order (>24)
filters, up to three GF9101's would allow a 72 tap FIR filter to
be configured without any additional hardware. In Figure
13, two GF9101's are cascaded together to obtain a 48 tap
filter. The data enters DATA_A_IN (device number 1) and
exits from DATA_B_OUT (device number 1). In device
number 2, the DATA_A_OUT bus is connected to
DATA_B_IN in order to feed the data back in to the B12
register of the same device. The contents of the
configuration register will be different for the two devices to
compensate for a three register delay introduced when two
GF9101's are cascaded to get a 48 tap filter. The
configuration register contents are shown in Table 11.
PIPELINE _OUT
COEF_ADDR
(6-0)
01
H
00
H
01
H
01
H
00
H
01
H
00
H
00
H
FB _SEL
CONFIGURE
ZERO
LOAD_EN
ENC
01
H
00
H
01
H
0 1 2 3 4 5 6 7 8 9 10
CLK_IN
ENA
ENB
SEL_A/B
A B A B A B A B A B
DATA_A_IN
B
PADDER
(A
23
x C
0
) + (A
22
x C
1
) + (A
21
x C
2
) +...+(A
13
x C
10
) + (A
12
x C
11
)
DATA
A
IN
DATA
B
OUT
C
0
Σ
x
x
x
x
x
A
0
A
1
C
1
C
2
C
10
C
11
A
10
A
13
A
21
A
22
A
11
A
2
A
12
A
23
PADDER
(A
0
x C
23
) + (A
1
x C
22
) + (A
2
x C
21
) +...+(A
10
x C
13
) + (A
11
x C
12
)
+
DATA
A
IN
DATA
B
OUT
C
23
Σ
x
x
x
x
x
A
0
A
1
A
2
C
22
C
21
C
13
C
12
A
10
A
12
A
13
A
21
A
22
A
23
A
11
(A
23
x C
0
) + (A
22
x C
1
) + (A
21
x C
2
) +...+(A
13
x C
10
) + (A
12
x C
11
)
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