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參數(shù)資料
| 型號(hào)： | GAL22V10B-15QP |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | EE PLD, 15 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | GAL22V10B-15QP |
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SSpecifications
GAL22LV10D
7
-5
MIN. MAX.
t
pd
2
t
co
2
t
cf
3
t
su
t
h
A
Input or I/O to Combinational Output
1
4
1
5
ns
A
Clock to Output Delay
1
3
1
3.5
ns
—
Clock to Feedback Delay
—
2.5
—
3
ns
—
Setup Time, Input or Feedback before Clock
↑
3
—
3.5
—
ns
—
A
Hold Time, Input or Feedback after Clock
↑
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
0
—
—
0
—
—
ns
MHz
167
143
f
max
4
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
182
—
154
—
MHz
A
Maximum Clock Frequency with
No Feedback
250
—
200
—
MHz
t
wh
4
t
wl
4
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
—
Clock Pulse Duration, High
2
—
2.5
—
ns
—
Clock Pulse Duration, Low
2
—
2.5
—
ns
B
Input or I/O to Output Enabled
1
5
1
6
ns
C
Input or I/O to Output Disabled
1
5
1
6
ns
A
Input or I/O to Asynchronous Reset of Register
1
4.5
1
5.5
ns
—
Asynchronous Reset Pulse Duration
4.5
—
5.5
—
ns
—
Asynchronous Reset to Clock
↑
Recovery Time
3.5
—
4
—
ns
—
Synchronous Preset to Clock
↑
Recovery Time
3.5
—
4
—
ns
-4
MIN. MAX.
UNITS
PARAMETER
TEST
COND
1
.
DESCRIPTION
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
I
Input Capacitance
5
pF
V
CC
= 3.3V, V
I
= 0V
C
I/O
I/O Capacitance
5
pF
V
CC
= 3.3V, V
I/O
= 0V
1) Refer to
Switching Test Conditions
section.
2) Minimum values for
t
pd and
t
co are not 100% tested but established by characterization.
3) Calculated from
f
max with internal feedback. Refer to
fmax Descriptions
section.
4) Refer to
fmax Descriptions
section. Characterized but not 100% tested.
COM
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
°
C, f = 1.0 MHz)
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| GAL22V10B-20LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
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