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參數(shù)資料
| 型號(hào)： | GAL22V10B-15QP |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | EE PLD, 15 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 223K |
| 代理商： | GAL22V10B-15QP |
Specifications
GAL22LV10
11
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note:
t
cf is a calculated value, derived by subtracting
t
su from
the period of fmax w/internal feedback (
t
cf = 1/
f
max -
t
su). The
value of
t
cf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to
t
cf +
t
pd.
f
max with No Feedback
Note:
f
max with no feedback may be less than 1/(
t
wh +
t
wl). This
is to allow for a clock duty cycle of other than 50%.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
f
max with External Feedback 1/(
t
su+
t
co)
Note:
f
max with external feedback is calculated from measured
t
su and
t
co.
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
f
max Descriptions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GAL22V10D-15QP | Electrically-Erasable PLD |
| GAL26CV12-15LJ | Electrically-Erasable PLD |
| GAL18V10-15D | ASIC |
| GAL18V10-15DI | ASIC |
| GAL18V10-15DM | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10B-20LD | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10B-20LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10B-20LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-20LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-20LR/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
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