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參數(shù)資料
| 型號(hào)： | GAL22V10B-15QP |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | EE PLD, 15 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 223K |
| 代理商： | GAL22V10B-15QP |
Specifications
GAL22LV10
12
*C
L
includes test fixture and probe capacitance.
TEST POINT
Z
0
= 50
, C
L
= 35pF*
FROM OUTPUT (O/Q)
UNDER TEST
+1.45V
R
1
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5ns 10% – 90%
1.5V
1.5V
See Figure
Output Load Conditions (see figure)
Test Condition
R
1
C
L
A
B
50
50
50
50
50
35pF
35pF
35pF
35pF
35pF
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
C
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from steady-state active
level.
GND to 3.0V
2.0ns 10% – 90%
1.5V
1.5V
See Figure
Output Load Conditions (see figure)
Test Condition
A
B
Active High
Active Low
C
Active High
Active Low
R
1
R
2
C
L
316
316
316
316
316
348
348
348
348
348
35pF
35pF
35pF
5pF
5pF
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+3.3V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
GAL22LV10D: Switching Test Conditions
GAL22LV10C: Switching Test Conditions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10B-20LD | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10B-20LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10B-20LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-20LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-20LR/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
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