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參數(shù)資料
| 型號： | FX980L6 |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 58/86頁 |
| 文件大?。?/td> | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
61
D/980/3
TxDataAccess
Title:
Tx Data path Access point.
Address:
$0x50 to $0x53 (mapped over 4 locations)
Function:
RW
Description:
This register block allows direct access to the Tx Data path values just after the gain, phase and
offset adjustment block. Both read and write operations are permitted. A read operation reads
the signal values on the I and Q channels. A write operation will write data to the data path just
before the 15-tap filter. To prevent normal Tx data overwriting this value the TxDPAccessSel bit
in the LoopBackCtrl register should be set active. The MSB read data register is buffered to
enable access to a discrete sample value (if this register was not buffered, data from different
sample periods could be in the MSB and LSB registers). Therefore the LSB register must be
read first for correct operation.
Bit
Name
Active State
Function
Address $0x50
7:0
TxDPIDataLSB
Data RW
Least significant 8 bits of the TxDPIData register. This
register must be read before its associated MSB register.
Address $0x51
7:4
RW
Reserved. Set these bits Low. Undefined on read.
3:0
TxDPIDataMSB
Data RW
Most significant 2 bits of the TxDPIData register.
Address $0x52
7:0
TxDPQDataLSB
Data RW
Least significant 8 bits of the TxDPQData register. This
register must be read before its associated MSB register.
Address $0x53
7:4
RW
Reserved. Set these bits Low. Undefined on read.
3:0
TxDPQDataMSB
Data RW
Most significant 2 bits of the TxDPQData register.
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