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參數(shù)資料
| 型號： | FX980L6 |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 31/86頁 |
| 文件大?。?/td> | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
37
D/980/3
AuxDacData
Title:
Auxiliary DAC Data registers
Address:
(Eight registers) $0x18 to $0x1F
Function:
RW
Description:
There are two input registers for each of the four auxiliary DACs. Writing to the AuxDac#LsbData
register writes the least significant two bits of DAC data.
Writing to the AuxDac#MsbData
register writes the most significant eight bits of DAC data and then passes all ten bits to the
appropriate DAC input (only if the RamDacActive bit is set Low for DAC 1).
If the
AuxDac#MsbData register is written while the AuxDac#LsbData register is left constant, the
converter may be treated as an 8-bit DAC.
Bit
Name
Active State
Function
Address $0x18
7:2
RW
Reserved. These bits should be set Low. Undefined on
read.
1:0
AuxDac1LsbData
Data RW
Writing to this address writes the least significant two bits
of the DacData1 register. These two bits may be read for
test purposes.
Address $0x19
7:0
AuxDac1MsbData
Data RW
Writing to this address writes the most significant eight
bits of the DacData1 register and updates DAC 1. This
register may also be read for test purposes.
Address $0x1A
7:2
RW
Reserved. These bits should be set Low. Undefined on
read.
1:0
AuxDac2LsbData
Data RW
Writing to this address writes the least significant two bits
of the DacData2 register. These two bits may be read for
test purposes.
Address $0x1B
7:0
AuxDac2MsbData
Data RW
Writing to this address writes the most significant eight
bits of the DacData2 register and updates DAC 2. This
register may also be read for test purposes.
Address $0x1C
7:2
RW
Reserved. These bits should be set Low. Undefined on
read.
1:0
AuxDac3LsbData
Data RW
Writing to this address writes the least significant two bits
of the DacData3 register. These two bits may be read for
test purposes.
Address $0x1D
7:0
AuxDac3MsbData
Data RW
Writing to this address writes the most significant eight
bits of the DacData3 register and updates DAC 3. This
register may also be read for test purposes.
Address $0x1E
7:2
RW
Reserved. These bits should be set Low. Undefined on
read.
1:0
AuxDac4LsbData
Data RW
Writing to this address writes the least significant two bits
of the DacData4 register. These two bits may be read for
test purposes.
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