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參數(shù)資料
| 型號： | FW804 |
| 英文描述： | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| 中文描述： | PHY的IEEE 1394A端口四線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 398K |
| 代理商： | FW804 |
18
Agere Systems Inc.
Data Sheet, Rev. 3
June 2001
Four-Cable Transceiver/Arbiter Device
FW804 PHY
IEEE
1394A
Internal Register Configuration
The PHY register map is shown below in Table 8.
Table 8. PHY Register Map for the Cable Environment
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0000
2
Physical_ID
R
PS
0001
2
RHB
IBR
Gap_count
0010
2
Extended (7)
XXXXX
XXXXX
Jitter
Total_ports
0011
2
Max_speed
Delay
0100
2
LCtrl
Contender
Pwr_class
0101
2
Resume_int
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Page_select
XXXXX
Register 0
Page_select
ISBR
Loop
Pwr_fail
Timeout
Port_event Enab_accel Enab_multi
0110
2
XXXXX
0111
2
Port_select
1000
2
1111
2
Register 7
Page_select
REQUIRED
XXXXX
RESERVED
Field
Size Type
Power Reset
Value
Description
Physical_ID
6
r
000000
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
When set to one, indicates that this node is the root.
Cable power active.
Root hold-off bit. When set to one, the force_root variable is
TRUE, which instructs the PHY to attempt to become the root
during the next tree identify process.
Initiate bus reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166
μ
s. This bit is self-clearing.
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of
IEEE
Standard 1394-1995 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY register map.
R
PS
RHB
1
1
1
r
r
0
—
0
rw
IBR
1
rw
0
Gap_count
6
rw
3F
16
Extended
3
r
7
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW804-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
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