參數(shù)資料
型號(hào)： FT232RL-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 7/43頁(yè)
文件大小： 0K
描述： IC USB FS SERIAL UART 28-SSOP
產(chǎn)品培訓(xùn)模塊： USB Introduction
USB-UART Interface Solutions
標(biāo)準(zhǔn)包裝： 1
系列： USBmadeEZ-UART
特點(diǎn)： USB 至 UART
通道數(shù)： 1，UART
FIFO's： 256 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 3.3 V ~ 5.25 V
帶自動(dòng)流量控制功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 634 (CN2011-ZH PDF)
配用： 768-1023-ND - MOD USB RS232 DEV/EVAL FT232RL
768-1022-ND - MOD USB UART MINI B DEV FT232R
768-1021-ND - MOD USB UART MINI DEV FT232R
768-1019-ND - MOD USB UART DEV FT232R
其它名稱： 768-1007-6
Copyright 2010 Future Technology Devices International Limited
15
Document No.: FT_000053
FT232R USB UART IC Datasheet Version 2.10
Clearance No.: FTDI# 38
4.2 Functional Block Descriptions
The following paragraphs detail each function within the FT232R. Please refer to the block diagram shown
in Figure 2.1
Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID
(PID), device serial number, product description string and various other USB configuration descriptors.
The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with the
internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is
available to system designers to allow storing additional data. The internal EEPROM descriptors can be
programmed in circuit, over USB without any additional voltage requirement. It can be programmed
using the FTDI utility software called MPROG, which can be downloaded from FTDI Utilities on the FTDI
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the
USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the
3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on
USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells
rather than to power external logic. However, it can be used to supply external circuitry requiring a
+3.3V nominal supply with a maximum current of 50mA.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB
reset detection conditions respectfully. This function also incorporates the internal USB series termination
resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This
provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference
clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal
Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz
clock reference is used by the USB DPLL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller and the
commands for controlling the functional parameters of the UART in accordance with the USB 2.0
specification chapter 9.
FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT
endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit
register under control of the UART FIFO controller. (Rx relative to the USB interface).
FIFO TX Buffer (256 bytes). Data from the UART receive register is stored in the TX buffer. The USB
host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device
data IN endpoint. (Tx relative to the USB interface).
UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and
TX buffers and the UART transmit and receive registers.
UART Controller with Programmable Signal Inversion and High Drive. Together with the UART
FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX
buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial
and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface.
Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller
also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485
transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking
is handled in hardware to ensure fast response times. The UART interface also supports the RS232
BREAK setting and detection conditions.
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