參數(shù)資料
型號: FT232HL-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 31/65頁
文件大?。?/td> 0K
描述: IC HS USB TO UART/FIFO 48LQFP
應(yīng)用說明: FT1248 Application Note
標(biāo)準(zhǔn)包裝: 1
通道數(shù): 1,UART
FIFO's: 4kb
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 1.98 V,2.97 V ~ 3.63 V
帶并行端口:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 768-1101-6
Copyright 2012 Future Technology Devices International Limited
37
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
MPSSE mode is enabled using the FT_SetBitMode D2xx driver command with a hex value of 0x02. A hex
value of 0x00 will reset the device. See application note AN135 – MPSSE Basics for more details and
examples.
The MPSSE command set is fully described in application note AN108 – Command Processor For
4.8.1
MPSSE Adaptive Clocking
The Adaptive Clock mode correlates the CLK signal with a return clock RTCK. This is a technique used by
ARM processors.
The FT232H will assert the TCK line and wait for the RTCK to be returned from the target device to
GPIOL3 line before changing the TDO (data out line).
FT2232H
ARM CPU
RTCK
TCK
TDO
GPIOL3
Figure 4.15 Adaptive Clocking Interconnect
TDO
TCK
RTCK
TDO changes on falling
edge of TCK
Figure 4.16: Adaptive Clocking waveform.
Adaptive clocking is not enabled by default.
For further details on MPSSE adaptive clocking please refer to AN_108
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