參數(shù)資料
型號(hào)： FT232HL-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 9/65頁(yè)
文件大小： 0K
描述： IC HS USB TO UART/FIFO 48LQFP
應(yīng)用說(shuō)明： FT1248 Application Note
標(biāo)準(zhǔn)包裝： 1
通道數(shù)： 1，UART
FIFO's： 4kb
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 1.98 V，2.97 V ~ 3.63 V
帶并行端口： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 768-1101-6
Copyright 2012 Future Technology Devices International Limited
17
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
3.5.4 FT232H can be configured as a Synchronous or Asynchronous Bit-Bang
Interface.
Bit-bang mode is an FTDI FT232H device mode that changes the 8 IO lines into an 8 bit bi-directional
data bus. This mode is enabled by sending a software command (FT_SetBitMode) to the FTDI driver.
When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in
Pin No.
Name
Type
Configuration Description
13,14,15,16,17,
18,19,20
ADBUS[7:0]
I/O
D7 to D0 bidirectional Bit-Bang parallel I/O
data pins
25
WRSTB#
OUTPUT
Write strobe, active low output indicates
when new data has been written to the I/O
pins from the Host PC (via the USB
interface).
26
RDSTB#
OUTPUT
Read strobe, this output rising edge indicates
when data has been read from the parallel
I/O pins and sent to the Host PC (via the USB
interface).
28
SIWU#
INPUT
The Send Immediate / WakeUp signal
combines two functions on a single pin. If
USB is in suspend mode (PWREN# = 1) and
remote wakeup is enabled in the EEPROM,
strobing this pin low will cause the device to
request a resume on the USB Bus. Normally,
this can be used to wake up the Host PC.
During normal operation (PWREN# = 0), if
this pin is strobed low any data in the device
RX buffer will be sent out over USB on the
next Bulk-IN request from the drivers
regardless of the pending packet size. This
can be used to optimize USB transfer speed
for some applications. Tie this pin to VCCIO if
not used.
Table 3.9 Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions
For functional description of this mode, please refer to section 4.6
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