參數(shù)資料
型號(hào)： FT2232HQ-TRAY
廠商： Future Technology Devices International Ltd
元件分類： 總線控制器
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： LEAD FREE, QFN-64
文件頁(yè)數(shù)： 4/63頁(yè)
文件大?。?/td> 1598K
代理商： FT2232HQ-TRAY
Copyright 2010 Future Technology Devices International Limited
12
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.10
Clearance No.: FTDI#77
3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface
The FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When
configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.5. To
enter this mode the external EEPROM must be set to make port A 245 mode. A software command (Set
Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel
synchronous FIFO mode. In this mode the B channel is not available as all resources have been switched
onto channel A. In this mode, data is written or read on the rising edge of the CLKOUT.
Channel A
Pin No.
Name
Type
FT245 Configuration Description
24,23,22,21,
19,18,17,16
ADBUS[7:0]
I/O
D7 to D0 bidirectional FIFO data. This bus is normally input unless
OE# is low.
26
RXF#
OUTPUT
When high, do not read data from the FIFO. When low, there is data
available in the FIFO which can be read by driving RD# low. When in
synchronous mode, data is transferred on every clock that RXF# and
RD# are both low. Note that the OE# pin must be driven low at least
1 clock period before asserting RD# low.
27
TXE#
OUTPUT
When high, do not write data into the FIFO. When low, data can be
written into the FIFO by driving WR# low. When in synchronous
mode, data is transferred on every clock that TXE# and WR# are both
low.
28
RD#
INPUT
Enables the current FIFO data byte to be driven onto D0...D7 when
RD# goes low. The next FIFO data byte (if available) is fetched from
the receive FIFO buffer each CLKOUT cycle until RD# goes high.
29
WR#
INPUT
Enables the data byte on the D0...D7 pins to be written into the
transmit FIFO buffer when WR# is low. The next FIFO data byte is
written to the transmit FIFO buffer each CLKOUT cycle until WR# goes
high.
32
CLKOUT
OUTPUT
60 MHz Clock driven from the chip. All signals should be synchronized
to this clock.
33
OE#
INPUT
Output enable when low to drive data onto D0-7. This should be
driven low at least 1 clock period before driving RD# low to allow for
data buffer turn-around.
30
SIWU
INPUT
The Send Immediate / WakeUp signal combines two functions on a
single pin. If USB is in suspend mode (PWREN# = 1) and remote
wakeup is enabled in the EEPROM , strobing this pin low will cause the
device to request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is strobed low any
data in the device TX buffer will be sent out over USB on the next
Bulk-IN request from the drivers regardless of the pending packet
size. This can be used to optimize USB transfer speed for some
applications. Tie this pin to VCCIO if not used. (Also see note 1, 2, 3
in section 4.12)
Table 3.5 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions
For a functional description of this mode, please refer to section 4.4
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